1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly to an electrically erasable and programmable non-volatile memory cell.
2. Description of Related Art
Non-volatile memories are commonly used for storing information which must be preserved even when the power supply for the memory is off. A particular type of non-volatile memory is an E2PROM (Electrically Erasable and Programmable Read-Only Memory). The E2PROM is typically formed by a matrix of memory cells, each one consisting of a floating gate MOS transistor. The transistor is programmed by injecting an electric charge into its floating gate; conversely, the transistor is erased by discharging its floating gate. The electric charge on the floating gate of the transistor modifies its threshold voltage, so as to define different logic values.
The E2PROMs have attained a widespread diffusion in the last few years (thanks to the fact that they can be programmed and erased directly in the field). Particularly, the E2PROMs are often used as embedded memories for logic circuits in several types of electronic devices (such as micro-controllers and smart cards). For this purpose, the E2PROM and the logic circuit are integrated in a single chip of semiconductor material.
However, the memory cells of the E2PROM substantially differ from the elements (such as MOS transistors) that are commonly used to implement the logic circuit. In detail, the MOS transistors require a single polysilicon layer to form their gates; conversely, the memory cells generally include two stacked polysilicon layers defining their floating gates and control gates, respectively. This structural difference increases the design and process complexity, with a detrimental impact on the manufacturing cost of the whole electronic device.
Moreover, operation of the memory cells requires (relatively) high voltages and/or currents. Particularly, the memory cells are typically programmed by Channel Hot Electron (CHE) injection. In this technique, a high voltage (for example, of 10V with respect to a reference voltage or ground) is applied between the drain and the control gate, so as to supply sufficient energy to some of the electrons flowing through a channel of the transistor to cause their injection into the floating gate. On the other hand, the memory cell is erased by Fowler-Nordheim tunneling, in which a high voltage (for example, 10V) is applied between the control gate and a substrate to remove the electric charge from the floating gate of the transistor.
In both cases, the voltages needed to program or to erase the E2PROM are far higher than a power supply voltage commonly used by the logic circuit (for example, 3-5V). This requirement adds further design complexity; moreover, charge pumps must be provided to generate the high voltages inside the chip (from the lower power supply voltage).
A different structure is described in WIPO International Patent Application Publication No. WO 98/47150. This document discloses a memory cell having a single polysilicon layer (for the floating gate). The transistor is formed in an insulated well; two diffusions define the control gate and an emitter of a lateral bipolar transistor (with the base and the collector consisting of the well and the channel, respectively). The floating gate extends over both the control gate and the emitter, so as to form two corresponding coupling capacitors. The memory cell is programmed by Substrate Hot Electron (SHE) injection. In this technique, the electrons to be injected into the floating gate are generated by the bipolar transistor (by forward biasing its base-emitter junction). The memory cell is always erased by Fowler-Nordheim tunneling, which takes place through the capacitor formed between the floating gate and the emitter.
The structure proposed in the cited document allows the use of a single process technology to manufacture both the E2PROM and the logic circuit. Moreover, the voltages required for programming the memory cells are substantially reduced.
However, this solution is not completely satisfactory. For example, the voltages needed to erase the E2PROM are still high and completely incompatible with the power supply voltage commonly used by the logic circuits.